A six-order wideband bandpass sigma-delta modulator

frequency 40MHz with 78dB Dynamic Range in a 0.35µm CMOS process. I. INTRODUCTION Oversampling bandpass A/D is widely used because of its increased accuracy and decreased analog front-end circuitries in transceiver systems. High frequency digital processing is more robust than its analog counterpart, and does not have the analog circuit imperfections. Digital IF extraction is also very beneficial since it adds the programmability to the system, for adapting to various standards. As shown in Fig.1, the higher IF frequency improves the suppression of the image signal, permitted by a non-ideal channel-selecting filter to enter in the signal bandwidth [1]. Therefore in this paper it has been tried to achieve a higher IF frequency and a reasonable resolution in the design of the wide band sigma-delta modulator. This paper describes a design and a behavioral simulation procedure of a fully integrated Switched Capacitor, Wideband, and Bandpass Sigma-Delta Modulator in a 0.35µm CMOS process. The modulator IF frequency is 40MHz, achieving 78dB Dynamic Range. In section II, the concepts of high order bandpass sigma-delta modulators are illustrated. In section III, the two-path architecture and low-pass filter technique are investigated. Finally the simulation results are summarized in section IV.